Transistors, and in particular, metal-oxide-semiconductor field-effect transistors (MOSFETs), offer many desirable switch characteristics. Nevertheless, some of their characteristics may render their usage problematic in certain contexts. For example, the manufacturing process for MOSFETs produces internal junctions between p-type and n-type silicon, yielding parasitic diodes that must be taken into account. Normally one of these parasitic diodes is shorted out by coupling one of the MOSFET terminals to the “body”, i.e., the bulk material of the semiconducting device. By convention, the terminal configured in this manner is designated as the source, while the terminal with the remaining parasitic diode is designated as the drain. Any failure to maintain the drain at a voltage substantially equal to or greater than the source results in excessive current flow through the parasitic diode, potentially resulting in damage to the device. This characteristic presents difficulties in switching applications where the voltage across the switch terminals is unknown or can change polarities.
A popular technique for addressing this difficulty is the use of an anti-series switch configuration, a configuration that employs two MOSFETS connected in series between the switch terminals with opposing orientations of their parasitic diodes. The intermediate node between the transistors can join their source nodes, or it can join their drain nodes. The intermediate source node configuration permits the use of a shared gate signal, whereas the intermediate drain node configuration necessitates individual gate signals for each transistor.
In applications requiring sensing of the switch terminal voltages (e.g., switching matrices, nondissipative balancing of battery banks), the anti-series switch is generally implemented as a four-terminal device. Specifically, when using the intermediate source node configuration, it is desirable to drive the shared gate terminal relative to the intermediate source node, thus requiring two terminals in addition to the switch terminals. Conversely, the intermediate drain node configuration requires two gate terminals in addition to the switch terminals, again yielding four terminals, and additionally requiring a second gate signal driver to boot. As the number of external anti-series switches increases, it becomes infeasible to provide four pins for each switch.
Various attempts have been made to implement the anti-series switch as a three terminal device by employing an intermediate source node configuration without a terminal connected to the intermediate node. Such configurations either suffer from poor switching performance or employ an undesirable number of external components to relate the gate terminal to the intermediate node voltage.